Hello! I am M.A. Mustafa from Ornate Pixels. With your skill development in smart LED TV repair in mind, I have discussed the crucial, fundamental aspects of repairing Sony and Samsung UA32M5570AULXL 40" LED TV that utilize the RT6936 IC in this article.
Several models of Samsung and Sony Bravia 40-inch TVs use the LSC400HN02-705 Samsung panel. To assist you in repairing this panel and to share some vital insights into LED TV display technology, I have published the complete schematic circuit diagram along with the RT6936 IC datasheet details. If you read this carefully, you will definitely find it highly beneficial for your daily benchmarking and repair work.
Hardware Overview and System Context
Before diving deep into the pin configurations, let us map out the exact board and system specifications for this hardware environment:
- Panel Number: LSC400HN02-705
- T-CON / Logic Board Number: 15Y_40GF11BMB7S4LV0.1
- Associated Primary PMIC: RT6929
The Core Responsibilities of the RT6936 IC
On this specific logic board, the RT6936 IC operates primarily as a supplementary or secondary Power Management IC (PMIC) combined with a Gate Drive / Level Shifter and Gamma function. Its main responsibility is to handle the demanding task of rapidly switching the gate lines or Thin-Film Transistor (TFT) pixels inside the display glass on and off.
To achieve this, it manages critical gate drive voltages. It generates the high-voltage VGH (ranging from 25V to 32V) and the negative voltage VGL (ranging from -5V to -10V) required by the panel's Gate COF (Chip-on-Film) or side COFs to keep image reproduction smooth and artifact-free.
The Hidden Digital Psychology of the RT6936 IC
When studying the schematic of the RT6936, the arrangement of its first few pins reveals a brilliant piece of digital engineering designed by silicon architects. If you look closely at Pin 1, Pin 2, and Pin 3, you will realize they are placed right next to each other for a structural reason.
Pin 1 (Bank_SEL) and the Pull-Down Safeguard
Pin 1 is labeled as Bank_Sel (Bank Selection Input), receiving a logic control signal directly from the main T-CON IC. In modern high-resolution panels, pixels are divided into distinct structural groups, or "banks," to support high-refresh-rate driving profiles. This signal determines which specific section or circuit block of the panel is active at any given millisecond.
The fascinating part is its hardware psychology: tracing the line reveals a physical resistor connected directly from Pin 1 to ground (GND). This is a classic Pull-Down Resistor setup. When the T-CON actively transmits a command, it sends a Logic '1' (typically 3.3V), forcing the IC to select the intended bank. However, when the T-CON is silent or initializing, this pull-down resistor firmly ties Pin 1 to a steady Logic '0' (0V). This prevents the pin from entering a "floating state" where random electromagnetic noise could trick the IC into misfiring.
The I2C Bus Proximity (SDA & SCL)
Right next to this selection line sits Pin 2 (SDA- Serial Data) and Pin 3 (SCL- Serial Clock). These two pins form the standard I2C communication bus, allowing the main processor to dynamically adjust internal registers, gamma levels, and operational settings inside the RT6936.
Why are they grouped so closely with Bank_SEL? Because all three lines are low-voltage, high-speed digital logic signals connecting to the same internal Digital Control Block of the silicon chip. Conversely, the other side of the IC houses high-voltage switching lines like LXN, LXP, and VON, which radiate significant electromagnetic interference (EMI). By grouping Bank_SEL, SDA, and SCL closely together on one side, the designers insulated the delicate digital dialogue from high-voltage spikes, ensuring zero data corruption during operation.
Vertical Clock Pulse Dynamics (Pins 4 to 8)
Pins 4, 5, 7, and 8 are tied directly to the core vertical timing system of the panel, labeled respectively as CPV1, CPV2, CPV3, and CPV4. Each of these lines carries a stable 3.1V signal.
When mapping these layout points on your schematic, the directional arrows must point into the IC (Input). These low-voltage Clock Pulse Vertical (CPV) signals originate inside the main T-CON chip. The RT6936 inputs these precise timing signals and uses its internal level shifters to amplify them using the high-voltage rails (VGH/VGL). This translated, high-amplitude energy is what ultimately exits the IC toward the panel as raw CKV signals to drive the pixel rows sequence by sequence.
Inter-IC Protection and Master-Slave Interlinking
A highly sophisticated feature of the 15Y_40GF11BMB7S4LV0.1 board design is the hardwired partnership between the secondary RT6936 IC and the primary RT6929 IC Schematic Circuit Diagram. They act as a coordinated team via specialized communication lines:
- Pin 9 (SEQ_OUT to RT6929 SEQ_IN): This pin acts as a sequence hand-off output. Once the RT6936 safely completes its internal startup phases and timing routines, it sends an outbound signal to the primary RT6929 to clear the next stage of system initialization. Because this originates here and goes outward, its schematic arrow points away from the IC (Output).
- Pin 37 (FAULT to RT6929 FAULT): This is the emergency system brake line. If a short circuit occurs in the panel gate lines or if an over-current condition develops under the RT6936's watch, this pin immediately shifts state to alert the primary RT6929 PMIC. The RT6929 can then trigger a full shutdown protection cycle to save the delicate panel glass from burning. This is an outbound protection indicator, so its schematic arrow points away from the IC (Output).
RT6936 Complete Schematic Circuit Diagram
To help you accurately trace lines and perform component-level isolation on the 15Y_40GF11BMB7S4LV0.1 board, utilize the verified schematic layout below during your diagnostic procedures.
Below is the RT6936 IC Schematic Circuit Diagram and its pin functions. This schematic circuit diagram is applicable for both RT6936A and RT6936 IC versions.
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| Figure 1: Verified RT6936 IC Schematic Circuit Diagram, Pinout Data and Voltage Details. |
RT6936 Deep Pin-by-Pin Analysis & Specifications (1 - 40)
To ensure a flawless reading experience on mobile devices without any broken layout alignment, here is the comprehensive structural analysis of all 40 pins of the RT6936 IC arranged in a clean, vertical reading format:
PIN 1: I/O_1 (From T-Con Bank_SEL) [Logic State: 0V / 3.3V]
This is the Bank Selection Control Input line running directly from the T-CON IC. It commands the level shifter to switch between different driving blocks. Built with an external pull-down resistor to ground to guarantee it safely reads a steady Logic '0' whenever the T-CON stops transmitting data.
PIN 2: SDA (Serial Data) [Digital Pulse: ~3.3V]
The dedicated I2C bidirectional data line is used for communicating configuration values, registry parameters, and dynamic settings between the master controller and the RT6936 internal logic engine.
PIN 3: SCL (Serial Clock) [Digital Pulse: ~3.3V]
The I2C synchronous clock input coordinates the timing of data packet transfers on the SDA line. Placed right next to PIN 1 and 2 to consolidate low-voltage digital operations and insulate them from high-voltage noise zones.
PIN 4: CPV1 (Clock Pulse Vertical 1) [Measured Voltage: 3.1V]
The vertical timing clock input 1 is sourced from the T-CON. Schematic direction arrows must point inward. This signal marks the shifting tempo for the panel’s primary vertical scanning rows.
PIN 5: CPV2 (Clock Pulse Vertical 2) [Measured Voltage: 3.1V]
The vertical timing clock input 2 is sourced from the T-CON. Acts as the secondary input reference channel to shift alternating gate arrays cleanly inside the glass structure.
PIN 6: Internal Connection / NC [--]
This pin represents an internal loop path or non-connected placeholder trace designated for sub-surface chip tracking architectures.
PIN 7: CPV3 (Clock Pulse Vertical 3) [Measured Voltage: 3.1V]
The vertical timing clock input 3 flows from the T-CON into the internal logic core to synchronize high-definition vertical scanning lines.
PIN 8: CPV4 (Clock Pulse Vertical 4) [Measured Voltage: 3.1V]
The vertical timing clock input 4. This rounds up the 4-phase vertical timing matrix needed to drive the panel smoothly without vertical ghosting artifacts.
PIN 9: SEQ_OUT to RT6929 SEQ_IN [Logic Output]
The tracking sequence hand-off line sends an authorization signal outward to the main RT6929 PMIC, signaling that the level shifter core is successfully initialized.
PIN 10: AGND (Analog Ground) [Measured Voltage: 0V]
The pristine ground return reference line is specifically designated for the IC's sensitive analog comparator modules and error amplifiers.
PIN 11: VIN (Operating Voltage Input) [Measured Voltage: e.g., 12V Main Rail]
The primary DC power supply input node that feeds the internal circuitry and powers up the core charging pumps of the IC.
PIN 12: LXN (Negative Switching Node) [Switching Waveform]
The active high-frequency switching terminal is paired with internal power MOSFETs to convert the positive VIN rail into the negative VGL subsystem.
PIN 13: I/O2 / VOFF (VGL) [Measured Voltage: -5V to -10V Base]
The crucial negative voltage generation node that supplies the essential bias needed to turn off the panel's TFT gate switches completely.
PIN 14: I/O3 / VSS [Measured Voltage: -7.6V]
A highly stable, regulated secondary negative reference line is utilized to balance internal operational baselines.
PIN 15: I/O4 / VSSP to Panel [Negative Output]
The filtered, clean negative voltage distribution track runs straight past the board boundaries onto the TFT panel row drivers.
PIN 16: I/O5 / STVP to Panel [Pulse Profile]
The Start Vertical Pulse Output. This high-amplitude signal initiates the scanning sequence of a brand-new image frame inside the display grid.
PIN 17: I/O6 / CKV_FB1 to Panel [Feedback Variable]
The diagnostic Clock Vertical Feedback terminal 1 that continuously samples panel capacitance and line distortions back to the IC.
PIN 18: I/O7 / CKV_FB2 to Panel [Feedback Variable]
The diagnostic Clock Vertical Feedback terminal 2 is designed to monitor real-time tracking variations on the secondary glass line matrix.
PIN 19: I/O8 / CKV-1 [High-Voltage Pulse Output]
The boosted Level Shifter Output Channel 1 delivers amplified vertical clocking shifts across the gate COF columns.
PIN 20: I/O9 / CKVCS1 [Control Node]
Clock Vertical Charge Sharing Node 1. This configuration point redistributes leftover electrical charges between clock transits to lower EMI and heating.
PIN 21: I/O-10 / CKB1 [High-Voltage Pulse Output]
Complementary Vertical Clock Bar Output 1 running in perfect reverse-phase alignment to the CKV-1 signal line.
PIN 22: I/O11 / CKV-2 [High-Voltage Pulse Output]
The boosted Level Shifter Output Channel 2 sends amplified high-swing scanning pulses into the display panel glass.
PIN 23: I/O12 / CKVCS2 [Control Node]
Clock Vertical Charge Sharing Node 2 helps neutralize thermal buildup during high-frequency vertical switching cycles.
PIN 24: I/O13 / CKB2 [High-Voltage Pulse Output]
Complementary Vertical Clock Bar Output 2 operating as the inverse signal companion to the primary CKV-2 transmission path.
PIN 25: I/O14 / CKV-3 [High-Voltage Pulse Output]
The boosted Level Shifter Output Channel 3 carries raw high-voltage pulses directly to the panel’s third horizontal gate sector.
PIN 26: I/O15 / CKVCS3 [Control Node]
Clock Vertical Charge Sharing Node 3 optimizing rise and fall response profiles during active panel operation.
PIN 27: I/O16 / CKB3 [High-Voltage Pulse Output]
Complementary Vertical Clock Bar Output 3 delivers out-of-phase balance directly to the glass row drivers.
PIN 28: I/O17 / CKV-4 [High-Voltage Pulse Output]
The boosted Level Shifter Output Channel 4 manages high-voltage pulse sequences over the final vertical routing groups.
PIN 29: I/O18 / CKVCS4 [Control Node]
Clock Vertical Charge Sharing Node 4, maintaining power efficiency across the complex gate driving network.
PIN 30: I/O19 / CKB4 [High-Voltage Pulse Output]
Complementary Vertical Clock Bar Output 4 completes the primary four-phase balanced drive configuration.
PIN 31: VON (VGH) [Measured Voltage: 25V to 32V]
The primary positive high-voltage rail connection provides the power required to open the TFT pixel switches across the screen.
PIN 32: LXP/CXP (Positive Switching Node) [Switching Waveform]
The high-frequency booster terminal is connected to inductive components to pump up the input voltage to the high-level VON rail state.
PIN 33: PGND (Power Ground) [Measured Voltage: 0V]
The high-current structural ground path is dedicated to isolating switching currents away from sensitive control lines.
PIN 34: GATE P [Drive Voltage Output]
The external P-Channel power MOSFET gate terminal controller manages power rail transitions inside the board ecosystem.
PIN 35: NTC2 (Thermal Sense 2) [Analog Sense Node]
The secondary connection terminal for the Negative Temperature Coefficient thermistor setup safeguards the board from thermal runaway.
PIN 36: NTC1 (Thermal Sense 1) [Analog Sense Node]
The primary connection terminal for tracking local component operating temperatures on the logic board.
PIN 37: I/O20 / FAULT to RT6929 FAULT [Logic Output]
The critical system emergency warning line. Tracing shows this signal traveling directly outward to the primary RT6929 PMIC. It flags a fault instantly if a short circuit is found, locking down the system to protect the board.
PIN 38: I/O21 / SEQ_OUT TO RT6929 IC [Measured Voltage: 5V]
The secondary high-level enabling signature output that locks into the RT6929 system matrix during normal sequencing routines.
PIN 39: I/O22 / From T-Con TRDY [Logic Input]
The T-CON Ready verification signal is coming directly into the RT6936 logic block, confirming the video processing chip is fully stable.
PIN 40: VL [Measured Voltage: 5V]
The internal low-dropout linear regulator output. It provides a localized 5V line to run the IC's internal micro-logic switches smoothly.
Diagnostic & Troubleshooting Insights
When an LSC400HN02-705 panel displays a black screen, abnormal timing lines, or cyclic restart behaviors, diagnostic focus should shift to the RT6936 IC parameters. Always start by verifying the presence of 5V at Pin 40 (VL) and your input rail at Pin 11 (VIN).
If these input voltages are regular, but your high-voltage outputs at Pin 31 (VON) or Pin 13 (VOFF) are missing, inspect Pin 37 (FAULT). If Pin 37 is pulled down or throws an active alert line to the primary RT6929, check for micro-shorts along the CKV1- CKV4 lines extending toward the display panel glass. Isolating these shorted paths will frequently revive panels stuck in protection standby modes without needing an entirely new logic replacement.
Keep this pinout datasheet and diagnostic scheme handy on your repair bench to tackle complex Samsung display restorations confidently!
How to Cut CKV and CKB Lines on LSC400HN02-705 Panel using RT6936 Logic Level Shifter IC (Panel Bypass Method)
When the Samsung LSC400HN02-705 panel encounters internal glass short circuits, it typically forces the RT6936 IC into protection mode, disabling the VGH and VGL outputs. To bypass this breakdown and revive the screen, professional technicians rely on track cutting. On this specific logic board, the signals are divided into pairs: CKV1, CKV2, CKV3, CKV4, and their complementary signals CKB1, CKB2, CKB3, CKB4 (labeled as CKB on the board text tracks).
Before making any modifications, use your digital multimeter to check which side of the panel has the lower resistance to ground—this pinpoints the shorted side (Left or Right). Once identified, use a sharp surgical blade under a magnifying glass to carefully isolate the tracks. You must Cut The CKV line and its corresponding CKB companion together as pairs (for example, cutting CKV1 and CKB1 simultaneously).
Always make clean, micro-cuts on only ONE side of the board pathways. Isolating these shorted pulse tracks removes the heavy load from the RT6936 level shifter, safely bringing back stable display graphics without replacing the entire glass panel.
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